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| HM624256A Series 262144-word x 4-bit High Speed CMOS Static RAM Description The Hitachi HM624256A is a high speed 1M Static RAM organized as 262,144-word x 4-bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high speed circuit designing technology. It is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit MPU. The HM624256A, packaged in a 400-mil plastic SOJ is available for high density mounting. Features * Single 5 V supply and high density 28-pin package (DIP and SOJ) * High speed Access time: 20/25/35 ns (max) * Low power dissipation Active mode: 350 mW (typ) Standby mode: 100 W (typ) * Completely static memory No clock or timing strobe required * Equal access and cycle time * Directly TTL compatible All inputs and outputs HM624256A Series Ordering Information Type No. HM624256AP-20 HM624256AP-25 HM624256AP-35 HM624256ALP-20 HM624256ALP-25 HM624256ALP-35 HM624256AJP-20 HM624256AJP-25 HM624256AJP-35 Access Time Package 20 ns 25 ns 35 ns 20 ns 25 ns 35 ns 20 ns 25 ns 35 ns 400 mil 28-pin plastic SOJ (CP-28D) 400 mil 28-pin plastic DIP (DP-28C) HM624256ALJP-20 20 ns HM624256ALJP-25 25 ns HM624256ALJP-35 35 ns 2 HM624256A Series Pin Arrangement A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS OE VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O 1 I/O 2 I/O 3 I/O 4 WE Pin Description Pin Name A0 - A17 I/O1 - I/O4 CS OE WE VCC VSS Function Address Input/output Chip select Output enable Write enable Power supply Ground 3 HM624256A Series Block Diagram A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 I/O2 I/O3 I/O4 Row decoder Memory array 512 x 2048 VCC VSS Input data control Column I/O Column decoder A0 A1 A11A12A13A14A15A16A17 CS WE OE Function Table CS H L L L OE X L H L WE X H L L Mode Not selected Read Write Write VCC Current I/O Pin I SB , I SB1 I CC I CC I CC High-Z Dout Din Din Ref. Cycle Read cycle (1) - (3) Write cycle (1) Write cycle (2) Note: X: H or L Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Note: Symbol Vin PT Topr Tstg Tbias Value -0.5 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85 *1 Unit V W C C C 1. Vin min = -2.0 V for pulse width 10 ns 4 HM624256A Series Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- -- Max 5.5 0 6.0 0.8 Unit V V V V 1. VIL min = -2.0 V for pulse width 10 ns DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM624256A-20 Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Standby power supply current (1) Symbol |ILI| |ILO | I CC I SB I SB1 Min -- -- -- -- -- Typ -- -- -- -- 0.02 *1 HM624256A-25/35 Min -- -- -- -- -- Typ*1 -- -- -- -- 0.02 Max 2.0 2.0 120 40 2.0 Unit Test Conditions A A mA mA mA VCC = max Vin = VSS to V CC CS = VIH VI/O = VSS to V CC CS = VIL, II/O = 0 mA, min cycle CS = VIH, min cycle CS V CC - 0.2 V 0 V Vin 0.2 V or Vin V CC - 0.2 V Max 2.0 2.0 150 60 2.0 I SB1*2 Output low voltage Output high voltage VOL VOH -- -- 2.4 -- -- -- 100*2 0.4 -- -- -- 2.4 -- -- -- 100*2 0.4 -- A V V I OL = 8 mA I OH = -4 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. L-version Capacitance (Ta = 25C, f = 1 MHz) Parameter Input capacitance Symbol Cin Min -- -- Input/output capacitance CI/O -- Max 5 6 8 *2 *3 Unit pF pF pF Test Conditions Vin = 0 V VI/O = 0 V Notes: 1. This parameter is sampled and not 100% tested. 2. SOJ package 3. DIP package 5 HM624256A Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * * * * * Input pulse levels: 0V to 3.0 V Input rise and fall time: 4 ns Input timing reference levels: 1.5 V Output timing reference levels: 1.5 V Output load: See figures +5V 480 Dout 255 30 pF *1 Dout 255 5 pF *1 +5V 480 Output load (A) Note: 1. Including scope and jig Output load (B) (For tCHZ, tOHZ, tCLZ, tOLZ, tWHZ and tOW) Read Cycle HM624256A-20 HM624256A-25 HM624256A-35 Parameter Read cycle time Address access time Chip select access time Chip selection to output in low-Z Output enable to output valid Output enable to output in low-Z Chip deselection to output in high-Z Chip disable to output in high-Z Output hold from address change Chip selection to power up time Chip deselection to power down time Symbol Min t RC t AA t ACS t *1 CLZ Max -- 20 20 -- 10 -- 10 10 -- -- 12 Min 25 -- -- 5 -- 0 0 0 5 0 -- Max -- 25 25 -- 12 -- 12 10 -- -- 15 Min 35 -- -- 5 -- 0 0 0 5 0 -- Max -- 35 35 -- 15 -- 15 10 -- -- 25 Unit ns ns ns ns ns ns ns ns ns ns ns 20 -- -- 5 -- *1 t OE t OLZ t *1 CHZ *1 0 0 0 5 0 -- t OHZ t OH t PU t PD Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled not 100% tested. 6 HM624256A Series Read Timing Waveform (1)*1 (WE = VIH) t RC Address t AA OE t OE t OLZ t ACS t CLZ Dout t OHZ t CHZ Valid Data t OH CS Notes: 1. Transition is measured 200 mV from state voltage with Load (B). This parameter is sampled and not 100% tested. Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) t RC Address t AA t OH Dout Valid Data t OH 7 HM624256A Series Read Timing Waveform (3)*1, *2 (WE = VIH, OE = VIL ) CS t ACS t CLZ Dout High Impedance t PU VCC supply I CC current I SB Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 2.Device is continuously selected, CS = VIL. 50 % Valid Data t PD High Impedance 50 % t CHZ Write Cycle HM624256A-20 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Output disable to output in high-Z Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Symbol Min t WC t CW t AW t AS t WP *2 *3 *4 HM624256A-25 Min 25 17 20 0 17 0 0 0 15 0 0 Max -- -- -- -- -- -- 10 15 -- -- -- HM624256A-35 Min 35 25 30 0 25 0 0 0 20 0 0 Max -- -- -- -- -- -- 10 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns Max -- -- -- -- -- -- 10 12 -- -- -- 20 15 16 0 15 0 0 0 12 0 0 t WR t OHZ t *4 WHZ t DW t *5 DH *1 t OW Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap (tWP) of a low CS and a low WE. 3. t WR is measured from the earlier of CS or WE going high to the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 8 HM624256A Series Write Timing Waveform (1) t WC Address t WR OE t CW CS t AS WE t OHZ Dout t WP t DW Valid Data Notes: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remain in a high impedance state. t DH *1 t AW Din Write Timing Waveform (2) (OE Low Fixed) t WC Address t CW CS *1 t WR t WP WE t AS t OH t WHZ t OW *2 *3 Dout t DW Din t DH Valid Data Notes: 1. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 2.Dout is the same phase of write data of this write cycle. 3.Dout is the read data of next address. 9 HM624256A Series Low VCC Date Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max Unit Test Conditions -- V CS V CC - 0.2 V, Vin V CC - 0.2 V or 0 V Vin 0.2 V Data retention current I CCDR -- 0 5 2 -- -- 50*1 -- -- A ns ms Chip deselect to data retention time t CDR Operation recovery time Note: 1. VCC = 3.0 V tR Low V CC Data Retention Timing Waveform Data retention mode V CC 4.5 V t CDR 2.2 V V DR CS 0V CS VCC - 0.2 V tR 10 HM624256A Series Package Dimensions HM624256AP/ALP Series (DP-28C) 34.70 35.56 Max Unit: mm 28 15 9.64 9.91 Max 1 0.89 1.27 Max 1.30 14 5.08 Max 10.16 0.51 Min 2.54 Min 2.54 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 HM624256AJP/ALJP Series (CP-28D) 18.17 18.54 Max 28 15 10.16 0.13 11.18 0.13 Unit: mm 1 0.74 14 3.50 0.26 0.21 2.40 + 0.24 - 1.30 Max 0.43 0.10 1.27 0.10 0.80 +0.25 -0.17 9.40 0.25 11 |
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